1. Field of the Invention
The present disclosure relates to a semiconductor device and a method of fabricating the same and, more particularly, to a semiconductor device including conductive lines with a fine line width and a method of fabricating the same.
2. Description of Related Art
In recent years, as the demand for smaller sized electronic appliances increases, an increasing number of methods for increasing the integration density of semiconductor devices are being developed. These methods include not only techniques for reducing the size of components of the semiconductor devices, but also techniques for efficiently disposing components of the semiconductor devices on surfaces such as, for example, a semiconductor substrate. For example, a semiconductor memory device, such as a dynamic random access memory (DRAM), includes a plurality of memory cell array regions and core regions disposed around the cell array regions. Each of the cell array regions includes a plurality of memory unit cells, each of which has a cell transistor, a cell capacitor, and an interconnection portion.
In order to increase integration efficiency, a technique for forming the cell transistor on a semiconductor device, stacking an interlayer insulating layer on the cell transistor, and forming the cell capacitor on the interlayer insulating layer has been widely used. Furthermore, source and drain regions of the cell transistor are connected to a lower electrode or bit line of the cell capacitor, and a gate electrode of the cell transistor is connected to a word line thereof. However, with a reduction in size of the cell transistor, it is increasingly difficult to dispose interconnection lines required for operating the cell transistor. That is, it is increasingly difficult to dispose bit lines and word lines required for operating a cell transistor as the size of the cell transistor is being continually reduced.
A method of disposing word lines and bit lines is disclosed in U.S. Pat. No. 7,009,208 B2 entitled “Memory Device and Method of Production and Method of Use Same and Semiconductor Device and Method of Production of Same” by Aratani et al (“Aratani”). According to Aratani, a plurality of word lines is disposed in a memory portion having a plurality of memory cells (i.e., a memory cell array region). In this case, the word lines extend in a first direction in order to form a contact portion in one side of the memory cell array region. In other words, the word lines extend only in one direction from the memory cell array region. Thus, a sufficient region for the contact portion may be secured owing to the word lines extending in one direction. However, Aratani suffers from a number of limitations. For example, because the word lines extend only in one direction from the memory cell array region, when the word lines have a line width smaller than the resolution limit in a lithography process, it may be difficult to secure a region for the contact region of the word lines.
Therefore, there may be a need to develop a new method of disposing interconnection lines, in order to secure a sufficient contact region and overcome shrinkage in line width of interconnection lines, such as word lines. The present disclosure is directed towards overcoming one or more limitations of the prior art method of disposing word lines and bit lines.